Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation, and method of forming semiconductor device assembly including same

ABSTRACT

A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps. A method of forming a semiconductor device assembly is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of application Ser. No.10/225,978, filed Aug. 22, 2002, pending.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to methods and apparatusfor bumping a wafer. In particular, the present invention relates tomethods and apparatus of bumping a wafer and stitch wire bonding to thebumps as well as resulting assemblies and systems.

[0004] 2. State of the Art

[0005] Chip-On-Board (“COB”) or Board-On-Chip (“BOC”) technology is wellknown and utilized for mechanically attaching and electricallyconnecting semiconductor dice directly to a carrier substrate such as aprinted circuit board (“PCB”). Electrical connection in COB and BOCassemblies may be effected using various techniques such as wirebonding, tape automated bonding, and flip-chip attachment. Similarly,semiconductor dice may be attached and electrically connected to acarrier substrate in the form of a lead frame, such as a conventionaldie paddle lead frame and a leads-over-chip (LOC) lead frame.

[0006] Wire bonding is generally preceded by attachment of asemiconductor die to a carrier substrate with an appropriate adhesive,such as an epoxy, silver solder or adhesive-coated film or tape segment.A plurality of fine wires is then attached individually to each bond padon the semiconductor die and extended and bonded to a correspondingterminal pad (or lead) of the carrier substrate. The assembly or atleast a portion of the semiconductor die then may be encapsulated with afilled polymer by transfer molding, injection molding, pot molding, orwith a mass of silicone or an epoxy in a so-called “glob top”encapsulation process.

[0007] There are several predominant types of wire bonding techniques,including aluminum wedge ultrasonic bonding and gold thermosonic orthermocompression stitch bonding. Although the gold thermosonic orthermocompression stitch bonding technique has an associated higher costin materials than the aluminum wedge bonding technique, the goldthermosonic bond is faster to form. For example, gold thermosonicbonders are capable of production speeds of ten wires/second compared tospeeds of aluminum wedge bonders of five wires/second.

[0008] As the sizes and pitches (spacing) of semiconductor die bond padshave continued to decrease in concert with ongoing miniaturization ofintegrated circuits, reduction of bond pad sizes has precluded the useof wirebonder capillaries to form stitch or wedge bonds on the bond padsdue to damaging contact of the capillary with the relatively fragile andnonresilient (typically a glass) passivation layer surrounding the bondpads on the active surface. While a tilted orientation of wirebondercapillary end surface to prevent passivation layer damage has beenproposed in U.S. Pat. No. 5,437,405 to Asanavest, this is not an idealsolution and the approach is still limited by ever-decreasing bond padsize. Accordingly, it has been proposed to form a ball bump or stud bumpof conductive material on a bond pad preliminary to actual wire bonding,and then to form a protruding stitch bond to the previously formed ballor stud bump at a safe elevation above the surface of the passivationlayer. U.S. Pat. No. 5,328,079 to Mathew et al. discloses forming aconductive bump with a wirebonder capillary to a bond pad of asemiconductor die and then subsequently stitch bonding to the bump toprotect the surrounding area of the passivation layer surface. However,individually forming conductive bumps on the bond pads on a wafer tofacilitate subsequent wire bonding thereto has proven to be neither costeffective nor time efficient.

[0009] Gold has been favored as a metal for stud bumping bond pads towhich gold wires are to be stitch bonded. Specifically, bumpingsemiconductor die bond pads with a stud bump, typically gold, isconventionally used to provide a preferred contact for gold thermosonicor thermocompression bonding, as a gold stud bump provides an excellentcontact for the gold wire, being easily bondable and providing a robustconnection. Further, a gold stud bump formed on a bond pad results in aconductive structure displaced above the relatively fragile passivationlayer surface of the die or wafer surrounding and at a substantiallyhigher elevation over the active surface than the bond pads and providesa bonding surface for contact by a wire bonding capillary without therisk of contacting and damaging the surrounding passivation layersurface.

[0010] Gold stud bumps are formed with a thermosonic orthermocompression capillary, wherein the wirebonder capillary forms andreleases a gold ball on each separate bond pad, individually andconsecutively, until each bond pad on a wafer receives a gold stud bump.Some wafers conventionally include as many as about 11,400 bond pads andthe 300 mm wafers now being implemented by the semiconductor industrywill greatly increase this number. The instruments and capillaryutilized for forming the gold bumps have optimum stud bumping speeds ofabout eight to ten balls/second. Thus, it would take approximately onehour to gold stud bump 2½ to slightly over 3 wafers having 11,400 bondpads each, depending on bumping speed. Since a wirebonder may have acapital cost in excess of one hundred thousand dollars, and acceptablebumped wafer throughput thus requires a large number of wirebonders inaddition to the process time involved, it will be appreciated that thecurrent approach to wafer bumping is less than optimum.

[0011] Therefore, it would be advantageous to form bumps on a wafer toenable the advantages of gold thermosonic or thermocompression bonding,but with greater throughput. It would also be advantageous to producebumps on a wafer to enable stitch bonding without the excessive materialcosts of gold stud bumps.

BRIEF SUMMARY OF THE INVENTION

[0012] The present invention relates to methods and apparatus forbumping wafers. The present invention is directed to providing asemiconductor die to be singulated from a bumped wafer to which bondwires may be stitch bonded without requiring prior formation of a goldstud bump. The semiconductor die includes an active surface and a backsurface, wherein the active surface includes bond pads thereon. The bondpads may be in locations of an original bond pad pattern, or may bererouted over the active surface of the semiconductor die usingconductive traces in the form of a so-called redistribution layer, orRDL. At least some, and typically all, of the bond pads on the activesurface of the semiconductor die include a plated bump formed thereon.The plated bumps include a nickel material and are located to facilitatea stitch bond thereto. The terms “plated bump” or “bump” according tothe present invention and as that term is used herein with reference tothe present invention is not to be construed as requiring or including aball or other protrusion, but rather encompasses a contact elementhaving at least a portion of its outer surface extending substantiallyparallel to an active surface of the semiconductor die and the bond padover which it is formed, such contact element exhibiting a substantiallyflat exposed surface. The contact element may further reside within theconfines of a passivation layer surrounding the bond pads or,optionally, protrude over the passivation layer.

[0013] In accordance with the present invention, the plated bumps areformed on bond pads of unsingulated semiconductor dice at the waferlevel. In particular, one or more wafers having the bond pads exposedthrough passivation layers on the active surfaces thereof are disposedin a bath of a nickel-containing solution to undergo an electrolessplating process in the bath and simultaneously form nickel-containingplated bumps on each of the bond pads on the one or more wafers. The oneor more wafers may then optionally be placed in another electroless bathof either a gold-containing solution or a palladium-containing solutionto form either a gold-containing cap or a palladium-containing cap,respectively, on the previously formed nickel-containing plated bump. Animmersion bath to plate a gold-containing cap of self-limiting thicknessmay also be employed in lieu of electroless plating. In any case, onewould employ an immersion bath prior to initiation of the electrolessplating to provide a basis for formation of the electrolessly depositedmetal. The wafer having the plated bumps formed on each of the bond padsmay then undergo a singulation process as known in the art to divide thewafer into individual semiconductor dice. In another process accordingto the present invention and in lieu of using the aforementionedelectroless baths, the plated bumps may be formed using an electrolyticprocess.

[0014] In one aspect of the present invention, the plated bumps may beformed such that upper surfaces of the bumps are displaced above thepassivation layer on the active surface of the wafer. The displacedheight of the bump upper surface may be, for example, about 0.2 micronsto about 0.5 microns above the passivation layer of the wafer. The uppersurfaces of the plated bumps may alternatively be substantially coplanarwith the upper surface of the passivation layer of the wafer.

[0015] In another aspect of the present invention, an individualsemiconductor die singulated from the wafer may be assembled in asemiconductor device assembly. In particular, a semiconductor die havingplated bumps thereon according to the present invention is attached tocarrier substrate pads, terminals or leads. Bond wires may then beextended between and bonded to the carrier substrate and to the platedbumps on the active surface of the semiconductor die.

[0016] In one exemplary semiconductor device assembly, at least some ofthe plated bumps are formed proximate a periphery on the active surfaceof the semiconductor die. With this arrangement, the back surface of thesemiconductor die is attached to the surface of the carrier substrate sothat bond wires may be extended between the peripheral plated bumps andthe conductive pads on the carrier substrate.

[0017] In another exemplary semiconductor device assembly, at least someof the plated bumps are centrally aligned on the active surface of thesemiconductor die. The carrier substrate in this semiconductor deviceassembly includes a slot defined therein and extends between the surfacehaving the conductive pads and an opposing, second surface. With thisarrangement, the active surface of the semiconductor die is attached tothe second surface of the carrier substrate so that the centrallyaligned plated bumps of the semiconductor die are exposed through theslot in the carrier substrate. The bond wires extend through the slot ofthe carrier substrate from the centrally aligned plated bumps to theconductive pads on the surface of the carrier substrate. Of course, thecarrier substrate may also comprise a lead frame, as known in the art.

[0018] In one aspect of the present invention, the plated bumps on thewafer may be prepared to optimize the pull strength of the bond wiressubsequently bonded to the plated bumps. Such optimized pull strengthmay be accomplished by cleaning the plated bumps prior to bonding thebond wires thereto using an argon plasma cleaning process. Such cleaningprocess removes unwanted matter from the plated bumps, which strengthensthe subsequently formed bonds between the plated bumps and the bondwires.

[0019] In another aspect, a semiconductor device assembly of the presentinvention is mounted to a circuit board in an electronic system, such asa computer system. In the electronic system, the circuit board is alsoelectrically connected to a processor device which electricallycommunicates with an input device and an output device as well as thesemiconductor device assembly of the present invention.

[0020] Other features and advantages of the present invention willbecome apparent to those of skill in the art through a consideration ofthe ensuing description, the accompanying drawings and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0021] While the specification concludes with claims particularlypointing out and distinctly claiming that which is regarded as thepresent invention, the advantages of this invention may be ascertainedfrom the following description of the invention when read in conjunctionwith the accompanying drawings, wherein:

[0022]FIG. 1 illustrates a simplified top view of a wafer depicting thewafer including rows and columns of semiconductor dice according to thepresent invention;

[0023]FIG. 2 illustrates a simplified cross-sectional side view of thewafer of FIG. 1 taken along section line 2-2, depicting the wafer havingplated bumps on the semiconductor dice according to the presentinvention;

[0024]FIG. 3 illustrates a partial cross-sectional side view of thewafer of FIG. 1, depicting a bond pad in an active surface of one of thesemiconductor dice in the wafer according to the present invention;

[0025]FIG. 4 illustrates a partial cross-sectional side view of thewafer of FIG. 1, depicting a nickel-containing plated bump formed on thebond pad, according to the present invention;

[0026]FIG. 5 illustrates a partial cross-sectional side view of a platedbump having a plated cap formed thereon, according to the presentinvention;

[0027]FIG. 6 illustrates a simplified side view of a semiconductordevice assembly, depicting a semiconductor die back bonded to a carriersubstrate with wire bonds extending therebetween according to thepresent invention;

[0028]FIG. 7 illustrates a simplified cross-sectional side view ofanother semiconductor device assembly, depicting a semiconductor diefront bonded to a carrier substrate with a slot with wire bondsextending through the slot and interconnected to both the semiconductordie and carrier substrate according to the present invention;

[0029]FIG. 8 illustrates a partial cross-sectional side view of athermosonic capillary bonding bond wire to the plated bump according tothe present invention;

[0030]FIG. 9 illustrates a partial cross-sectional side view of a bondwire stitch bonded to the plated bump according to the presentinvention; and

[0031]FIG. 10 illustrates a block diagram of the semiconductor deviceassembly of the present invention interconnected to an electronicsystem.

DETAILED DESCRIPTION OF THE INVENTION

[0032] Embodiments of the present invention will be hereinafterdescribed with reference to the accompanying drawings. It would beunderstood that these illustrations are not to be taken as actual viewsof any specific apparatus or method of the present invention, but aremerely exemplary, idealized representations employed to more clearly andfully depict the present invention than might otherwise be possible.Additionally, elements and features common between the drawing figuresretain the same or similar numerical designations.

[0033]FIGS. 1 and 2 illustrate respective top and side views of a wafer110 having plated bumps 130 formed thereon in accordance with thepresent invention. The wafer 110 is preferably formed from silicon, butmay be formed from germanium, gallium arsenide, indium phosphide or anyother known semiconducting material, the electrical conductivity andresistivity of which lie between those of a conductor and an insulator.As used herein, the term “wafer” contemplates and encompasses not onlyconventional wafers but also other bulk substrates including a layer ofsemiconductor material including silicon-on-insulator (SOI) substrates,silicon-on-glass (SOG) substrates, silicon-on-sapphire (SOS) substrates,etc.

[0034] Wafer 110 includes multiple, unsingulated semiconductor dice 116in an array of columns and rows, each distinguished by intervening linesor “streets” 118. The wafer 110, and thus each of the multiplesemiconductor dice 116, includes an active surface 112 and a backsurface 114. According to the present invention, the active surface 112of the wafer 110 includes plated bumps 130 formed thereon. The platedbumps 130 are sized and configured for wire bonding bond wires thereto,specifically by stitch bonding. Such a wire bonding process may be, andtypically is, employed in a process subsequent to separating or“singulating” the wafer into multiple semiconductor dice (partial wafer)or individual, singulated semiconductor dice 116.

[0035] FIGS. 3-5 illustrate an exemplary method that may be used forforming the plated bumps 130 on the active surface 112 of the wafer 110.Referring first to FIG. 3, a simplified, enlarged partialcross-sectional view of the wafer 110 and a bond pad 120 of asemiconductor die 116 thereof is illustrated. The active surface 112 ofthe wafer 110 includes a passivation layer 124 with openings 126 definedtherein, exposing bond pads 120. Each of the openings 126 in thepassivation layer 124 may thus expose a bond pad 120 and, specifically,an exposed upper surface 122 thereof.

[0036] Bond pads 120 may be formed of any known electrically conductivematerial; however, bond pads 120 are typically formed of aluminum or analloy thereof. The bond pads 120 interconnect to integrated circuitry(not shown) formed in the active surface 112 of wafer 110 on each of therespective semiconductor dice 116 fabricated on the wafer 110. Thepassivation layer 124 may comprise one or more layers of any knownnonconductive dielectric-type material, such as silicon dioxide, BSG,PSG, BPSG or a ceramic. The passivation layer 124 electrically isolatesadjacent bond pads 120 and the integrated circuitry in active surface112 under the bond pads 120 to prevent short-circuiting and providesmechanical and environmental protection for the integrated circuitry.

[0037]FIG. 4 illustrates formation of a plated bump 130 on the exposedupper surface 122 of the bond pad 120. Plated bumps 130 may besubstantially simultaneously formed on each of the bond pads 120 on thewafer 110 through an electroless plating process. The plated bump 130includes a plated layer 132 formed from any known plated material. It iscurrently preferred that the plated layer 132 comprise nickel or analloy thereof. The electroless plating process provides deposition ofmetal from a chemical solution, usually at elevated temperatures,without an electrical current flowing as present in an electrolyticplating process. One suitable chemical solution that may be used forforming the plated bumps 130 may comprise a sodium hypophosphite nickelsolution, using about 2 to 12% nickel at about a 90° C. process (bath)temperature. However, any commercially available electroless orelectrolytic plating bath will serve the purpose. The chemical solutionis provided in a bath in which up to approximately fifty wafers, ormore, may sit immersed in a single plating cycle. A plating cycle maylast approximately fifteen to sixty minutes and produce a plated layer132 of nickel of about five to no more than about ten microns thickness.It is generally best not to exceed ten microns thickness of nickel, asan aluminum bond pad 120 of, for example, 100 μm by 100 μm in X-Ydimensions (parallel to the plane of wafer 110) which is in directcontact with the plated layer 132 of nickel is also in direct contactwith a glass passivation layer 124 which is, in turn, directly incontact with the silicon of wafer 110. The plated nickel, when annealed,contracts and places a shear force on the underlying silicon and cause aphenomenon termed “cratering,” and restricting the thickness of platedlayer 132 to less than ten microns will avoid such damage. Suitableproducts for conducting the electroless plating process on the wafers110 to form the plated bumps 130 thereon are offered commercially byPackaging Technology in Nauen, Germany and Shipley Ronal Electronic andIndustrial Finishing Division of Rohm and Haas Company.

[0038]FIG. 5 illustrates forming a plated cap 134 over the plated layer132. The plated cap 134 may be formed utilizing an electroless processas described above. The plated cap 134 may be formed of any known platedmaterial, such as, for example, gold or palladium, so long as the platedcap provides a suitable material for bonding to the material of bondwires. Although palladium may be used, utilizing gold to form the platedcap 134 may be preferred since bond wires are typically gold wires,which would provide gold-to-gold bonding adhesion. In one example, aplated cap 134 of gold may be formed to about a 0.2 to 0.8 micronthickness over plated layer 132. A suitable electroless gold platingtechnology is available at least from Packaging Technology.Alternatively, a plated cap of gold may be formed by immersion platingto a lesser, self-limiting thickness of about 0.05 micron. Formation ofplated cap 134 may be optionally implemented, is not believed by theinventors to be required for practice of the present invention and isnot to be taken as a limitation thereof.

[0039] As noted above, plated bumps 130 (optionally capped) may beformed on the bond pads 120 of the wafer 110 through the electrolessplating process or processes. The electroless plating process providesgreatly increased throughput, wherein plated bumps 130 may be formedsubstantially simultaneously on up to at least fifty wafers in a singlebatch in the hour's time it takes to conventionally form gold studbumps, individually and sequentially, on each of the bond pads of onlytwo or three wafers. Further, an upper surface of the plated bumps 130may be displaced above the passivation layer on the wafer surface toprevent contact by the wirebonder capillary and damage to thesurrounding region of the passivation layer proximate the plated bump130 when wire bonding thereto. Thus, the present invention providesplated bumps 130 configured to provide a bonding structure on each ofthe semiconductor dice in the wafer in a process which is less expensiveand substantially faster than conventional stud bumping processes. As analternative to the electroless plating process, the plated bumps 130 maybe formed through an electrolytic plating process utilizing techniqueswell known in the art.

[0040] In another aspect of the present invention, it has been found tobe advantageous to conduct a brief argon plasma cleaning process on theplated bumps 130 prior to wire bonding. Such plasma cleaning has beenfound to increase the pull strength of the wire bonds to the platedbumps 130. For example, after conducting an argon plasma cleaningoperation of 120 seconds on plated bumps comprising a 5 micronelectroless-plated nickel layer 132 with a 0.05 micron immersion-platedcap 134, bond wires bonded to the plated bumps 130 exhibited a robustpull strength of 10.5 grams. In comparison, without the plasma cleaning,the pull strength to similarly formulated and configured plated bumps130 exhibited a far lesser pull strength of approximately 4.5 grams. Inaddition, after cleaning, nearly all of the bond wedge remains on theplated bump 130 and the wire break occurs at the expected location wherethe wire and heel of the bond connect, which is the weakest point of thewire. Further, a number of wire bonds effected after cleaning were sostrong that the wire broke midspan during pull testing. Thus, an argonplasma cleaning process on the plated bumps 130 may be conducted tooptimize the pull strength between the bond wires and the plated bumps130. An oxygen plasma may also be used for cleaning the plated bumps130.

[0041]FIGS. 6 and 7 are illustrative examples of two respectivesemiconductor device assembly arrangements, wherein wire bondingtechniques may be employed in conjunction with the present invention.Prior to wire bonding, the wafer 110 is diced or singulated intoindividual semiconductor dice 116. Such a singulation process may beaccomplished by any known and suitable means for separating thesemiconductor dice, such as by sawing or scribing the wafer along linesor streets 118 (see, FIG. 1) or by cutting along the lines with a laser.The singulated semiconductor dice 116 are then prepared for die attach,wherein a singulated semiconductor die may be attached to a carriersubstrate such as an interposer, printed circuit board or lead framepreliminary to wire bonding.

[0042] Referring first to semiconductor device assembly 260 in FIG. 6, asemiconductor die 210 (which may, of course, comprise one of singulatedsemiconductor dice 116) having an active surface 212 and a back surface214 is back bonded using, for example, an epoxy, silver solder oradhesive-coated tape segment to a first surface 242 of a carriersubstrate 240. The carrier substrate 240 may include conductive pads 246on the first surface 242 thereof. Carrier substrate 240 may be formedfrom any suitable type of substrate material known in the art, such asbismaleimide triazine (BT) resin, ceramics, FR-4 or FR-5 materials. Withthis arrangement, the exposed surfaces of peripherally located bond padsbearing plated bumps 230 according to the present invention on theactive surface 212 of the semiconductor die 210 are oriented upwardly.The semiconductor device assembly 260 may then undergo a wire bondingprocess, wherein bond wires 23 are extended between the plated bumps 230on the semiconductor die 210 and conductive pads 246 on the carriersubstrate 240. After such a wire bonding process, the semiconductordevice assembly 260 may be encapsulated as shown schematically with adielectric encapsulation material 256 as known in the art and aspreviously mentioned to encapsulate the active elements of thesemiconductor die 210, namely, the active surface 212, plated bumps 230and bond wires 23.

[0043]FIG. 7 illustrates another semiconductor device assembly 360,wherein the semiconductor die 310 (which may, of course, comprise one ofsingulated semiconductor dice 116) is bonded with its active surface 312toward to the carrier substrate 340. Bond pads bearing plated bumps 330according to the present invention may be centrally aligned in one ormore rows on the active surface 312 thereof. In this semiconductorassembly 360, the carrier substrate 340 defines an opening in the formof slot 348 that extends from a first surface 342 to a second surface344 of the carrier substrate 340 and is of sufficient width and lengthto expose the centrally aligned plated bumps 330 on the semiconductordie 310. With this arrangement, the semiconductor die is bonded so thatthe plated bumps 330 are exposed through the slot 348 in the carriersubstrate 340. Bond wires 33 may then be extended between the platedbumps 330 on the semiconductor die 310 and conductive pads 346 on thesecond surface 344 of the carrier substrate 340 through slot 348. Theplated bumps 330, bond wires 33 and the exposed active surface 312 ofthe semiconductor die 310 may then be covered with a dielectricencapsulation material 356 as schematically shown for protectionthereof, as known in the art. Similarly, the back side 314 ofsemiconductor die 310 may be encapsulated.

[0044] Turning to FIGS. 8 and 9, there is illustrated a thermosonic wirebonding process for stitch bonding to plated bumps 230 on asemiconductor die 210 in an exemplary semiconductor device assembly,such as semiconductor device assembly 260 as illustrated in FIG. 6.Referring first to FIG. 8, a bond wire 23 may extend through a wire bondcapillary 270 to the plated bump 230 to stitch bond the bond wire 23 tothe plated bump 230. The bond wire 23 may be of any conductive materialsuitable for a thermosonic wire bonding process, but is preferably gold.As the wire bond capillary 270 extends the bond wire 23 to the platedbump 230, the wire bond capillary 270 places a load on the bond wire 23against the plated bump 230 transverse to the active surface 212 ofsemiconductor die 210 while simultaneously ultrasonically exciting thebond wire 23 and specifically the portion thereof in contact with platedbump 230. In response to the combination of load and ultrasonic powerapplied to the bond wire 23, the bond wire 23 and plated bump 230 join,after which the portion of bond wire 23 still carried by wire bondcapillary 270 is broken away by pulling, leaving a wedge-shaped stitchbond, as shown in FIG. 9.

[0045] Since the plated bumps 230 are formed to be at least coplanarwith the passivation layer 224 and desirably formed to extend to aheight slightly above the surrounding passivation layer on activesurface 212 of the semiconductor die 210, the relatively fragile,non-resilient passivation layer 224 surface area and integratedcircuitry thereunder in the region surrounding the plated bumps 230 issubstantially removed from contact by the capillary 270 in the stitchbonding process. The height that the plated bumps 230 extend above thepassivation layer 224 disposed over active surface 212 of thesemiconductor die 210 may be about 0.2 microns to about 2.5 microns, orany other suitable height to protect the active surface 212 of thesemiconductor die 210. Obviously, the thickness of the nickel portion ofthe plated bumps 230 may be widely varied to accommodate differentthicknesses of a passivation layer 224. For a 1 μm depth passivationlayer, it is contemplated that a 5 μm, a 1.5 μm or even a 1.2 μm thickplated bump 230 may suffice to prevent contact of the wire bondcapillary 270. It is contemplated that plated bump 230, after attaininga level with the exposed outer surface of passivation layer 224, mayextend thereover as it increases in height, although this is notrequired or even necessarily desired, due to the widely differingcoefficients of thermal expansion (CTE) of the two materials.

[0046] As illustrated in block diagram form in drawing FIG. 10,exemplary semiconductor device assemblies 260 or 360 with plated bumpsand stitch bonds according to the present invention may be mounted to acircuit board 410 in an electronic system 400, such as a computersystem. In the electronic system 400, the circuit board 410 may beconnected to a processor device 420 which communicates with an inputdevice 430 and an output device 440. The input device 430 may comprise akeyboard, mouse, joystick or any other type of electronic input device.The output device 440 may comprise a monitor, printer or storage device,such as a disk drive, or any other type of output device. The processordevice 420 may be, but is not limited to, a microprocessor or a circuitcard including hardware for processing instructions for the electronicsystem 400. Additional structure for the electronic system 400 isreadily apparent to those of ordinary skill in the art.

[0047] While the present invention has been disclosed in terms ofcertain preferred embodiments and alternatives thereof, those ofordinary skill in the art will recognize and appreciate that theinvention is not so limited. Additions, deletions and modifications tothe disclosed embodiments may be effected without departing from thescope of the invention as claimed herein. Similarly, features from oneembodiment may be combined with those of another while remaining withinthe scope of the invention.

What is claimed is:
 1. A method of bumping wafers, comprising: providingat least one wafer having an active surface and a back surface, theactive surface having bond pads exposed thereon through a passivationlayer; and disposing the at least one wafer in at least one bathincluding a nickel material to form a nickel-containing bump on each ofthe exposed bond pads.
 2. The method of claim 1, wherein disposingcomprises disposing the at least one wafer in at least one of anelectroless bath and an electrolytic bath.
 3. The method of claim 1,wherein disposing comprises disposing multiple wafers simultaneously inthe at least one bath.
 4. The method of claim 1, further comprisingdisposing the at least one wafer in at least another bath including agold material to form a gold-containing cap over each of thenickel-containing bumps.
 5. The method of claim 1, further comprisingdisposing the at least one wafer in at least another bath including apalladium material to form a palladium-containing cap over each of thenickel-containing bumps.
 6. The method of claim 1, wherein disposingcomprises forming the nickel-containing bumps with an outer surfacethereof displaced above an outer surface of the passivation layer. 7.The method of claim 1, wherein disposing comprises forming thenickel-containing bumps with an outer surface thereof substantiallycoplanar with an outer surface of the passivation layer.
 8. The methodof claim 1, wherein forming comprises forming the nickel-containingbumps with an outer surface thereof displaced above an outer surface ofthe passivation layer approximately 0.2 microns to 2.5 microns.
 9. Amethod of forming a semiconductor device assembly, the methodcomprising: providing at least one semiconductor die having an activesurface with bond pads formed thereon and a back surface, the bond padsbeing exposed through a passivation layer and each of the bond padsincluding a nickel-containing bump formed thereon; providing a carriersubstrate having conductive portions exposed on a surface thereof; andattaching the at least one semiconductor die to the surface of thecarrier substrate in a location and orientation exposing thenickel-containing bumps on the bond pads; and bonding bond wires to thenickel-containing bumps on the active surface and to the conductiveportions of the carrier substrate without contacting the passivationlayer with a wire bond capillary.
 10. The method of claim 9, whereinproviding the at least one semiconductor die comprises forming each ofthe nickel-containing bumps with an outer surface thereof displacedabove an outer surface of the passivation layer.
 11. The method of claim9, wherein providing the at least one semiconductor die comprisesforming each of the nickel-containing bumps with an outer surfacethereof substantially coplanar with an outer surface of the passivationlayer.
 12. The method of claim 9, wherein providing the at least onesemiconductor die comprises forming each of the nickel-containing bumpswith an outer surface thereof displaced above an outer surface of thepassivation layer approximately 0.2 microns to 2.5 microns.
 13. Themethod of claim 9, wherein providing the at least one semiconductor diecomprises providing the at least one semiconductor die with at leastsome of the nickel-containing bumps proximate a periphery of the activesurface thereof.
 14. The method of claim 13, wherein attaching comprisesattaching the back surface of the at least one semiconductor die to thesurface of the carrier substrate.
 15. The method of claim 9, whereinproviding the at least one semiconductor die comprises providing the atleast one semiconductor die with at least some of the nickel-containingbumps centrally aligned on the active surface thereof.
 16. The method ofclaim 15, wherein providing the carrier substrate comprises providingthe carrier substrate with a slot defined therein, wherein the slotextends between the surface of the carrier substrate and an opposing,second surface of the carrier substrate, and wherein attaching comprisesattaching the active surface of the at least one semiconductor die tothe second surface of the carrier substrate so that thenickel-containing bumps are exposed through the slot.
 17. The method ofclaim 9, further comprising encapsulating at least the nickel-containingbumps and the bond wires with a dielectric encapsulant.
 18. A method ofpreparing wafers for bonding bond wires thereto, the method comprising:providing at least one wafer having an active surface and a backsurface, the active surface having bond pads exposed thereon through apassivation layer; disposing the at least one wafer in at least one bathincluding a nickel material to form nickel-containing bumps on each ofthe exposed bond pads.
 19. The method of claim 18, further comprisingcleaning the nickel-containing bumps.
 20. The method of claim 19,wherein cleaning comprises performing an argon plasma cleaning.
 21. Themethod of claim 18, wherein disposing comprises disposing the at leastone wafer in at least one of an electroless bath and an electrolyticbath.
 22. The method of claim 21, wherein disposing comprises disposinga plurality of wafers simultaneously.
 23. The method of claim 18,further comprising disposing the at least one wafer in at leat anotherbath including a gold material to form a gold-containing cap over eachof the nickel-containing bumps.
 24. The method of claim 18, furthercomprising disposing the at least one wafer in at least another bathincluding a palladium material to form a palladium-containing cap overeach of the nickel-containing bumps.
 25. The method of claim 18, whereindisposing comprises forming the nickel-containing bumps with an outersurface thereof displaced above an outer surface of the passivationlayer.
 26. The method of claim 18, wherein disposing comprises formingthe nickel-containing bumps with an outer surface thereof substantiallycoplanar with an outer surface of the passivation layer.
 27. The methodof claim 18, wherein disposing comprises forming the nickel-containingbumps with an outer surface thereof displaced above the outer surface ofthe passivation layer approximately 0.2 microns to 2.5 microns.